1. Field of the Invention
The invention relates to a non-volatile storage cell of the metal-ferroelectric-semiconductor type and to a memory have such storage cells.
2. Brief Description of Related Art
Existing semiconductor memories are subdivided into two categories as a function of whether or not the stored information disappears when the power supply of the memory is interrupted. These memories are given different names, so that there are volatile memories (also known as dynamic memories) and non-volatile memories (also known as static memories).
In many cases non-volatile memories are read-only memories or ROM's. In such memories the information is written once and for all and cannot be modified. Among the read-only memories there are also programmable read-only memories or PROM's, as well as electrically erasable programmable read-only memories or EEPROM's, for which it is possible to modify the information state, but this can only take place a limited number of times, the information modification taking a long time. Consequently such memories are generally used in applications such as the storage of system programs in computers. In all other applications use is made of dynamic or volatile memories.
The presently existing non-volatile semiconductor memories essentially use the principle of charge storage by the injection of carriers (electrons or holes) into a dielectric. These charges are stored either in a conductive electrode embedded in the dielectrics (floating electrodes, SAMOS/FLOTOX structures), or at an interface between two dielectrics (MIOS structure). Such non-volatile memories are described on pp. 496 to 506 of the second edition of the publication "Physics of semiconductor devices" published by S. H. SZE and also in the chapter entitled "VLSI Electrically Erasable Programmable Read-Only Memory", of VLSI Handbook written by S. K. LAY and V. K. DHAM and published by Academic Press in 1985.
The state of the stored charge determines the binary 0 or 1 state of the information stored in the individual memory point. The information, i.e. the charge, is then read by the field effect created in the underlying semiconductor. Making the semi-conductor surface zone inverting or accumulating makes a MOS-type device conductive or non-conductive and its gate electrode is placed above the zone where the charges are stored.
Thus, the principle of writing information into such memories requires the injection of carriers into a dielectric. However, no matter what the carrier injection mode, the charge accumulation process is slow. A writing or erase cycle takes approximately or even more than 10 microseconds. Moreover, the injection leads to irreversible damage within the dielectric, in the form of trapped charges which gradually shield the stored charge, so as to limit the number of cycles to below 10.sup.6 and this is in the best possible case. The second document referred to hereinbefore, i.e. VLSI Handbook, relatively accurately describes this injection of carriers into a dielectric.
Finally, existing low cost, high density EPROM's are not electrically erasable and flash EEPROM's can only be erased blockwise. In order to obviate a certain number of these disadvantages, a novel technology has been recently proposed which makes use of ferroelectric effects. It is based on the use of metal-ferroelectric-metal capacitors for storing the information. The document entitled "A new memory technology is about to hit the market", in Revue Electronics of 18.2.1988 describes this novel technology. In its simplest version, with a conventional transistor is associated a capacitor of the aforementioned type, in accordance with the electronic diagram of FIG. 2A showing a so-called FRAM cell.
The programming and reading of said FRAM cell takes place in identical manner to that of a DRAM cell, whose electrical diagram is shown in FIG. 1. For such cells, the bit line BL is polarized for writing a "1" and is not polarized for writing a "0", the transistor T being made conductive during the programming of the cell by the polarization of the write line WL.
It is pointed out that a ferroelectric material has the property of a polarization state which varies with the electric field applied according to a hysteresis cycle and as shown in FIG. 3D.
From it can be deduced the following properties. There is a residual polarization P inducing an image charge Q on the electrodes (Q=P) in the absence of an electric field. This residual polarization is dependent on the history of the charges previously applied, if a strong electric field has been applied and which exceeds a certain value referred to as a coercive field. The polarization is positive, whereas it is negative if the electric field is negative.
The charge displaced during a voltage step from 0 to +V (or to -V) will depend on the state of the ferroelectric, provided that V exceeds the value of the coercive field. It is also possible to have a 0 image charge, although the field is not 0, namely by applying Gaussian distribution, i.e. ##EQU1## and then by making Q=0 in the case where E is such that P(E)=-.epsilon..sub.o E.
In the most widespread memory version using a metal-ferroelectric-metal capacitor, the information is read by subjecting the capacitor to a voltage step, so that the coercive field is exceeded. As a function of the initial polarization state, the ferroelectric will or will not be switched into the opposite polarization state.
The charge quantity displaced will be greater in the case of switching. It will then be possible to read the state of the memory point as a result of a current amplification circuit on the bit line able to discriminate the charge read with respect to a predetermined threshold. At least if the switching has been noticed, it is necessary to restore the ferroelectric to its initial state by a new voltage step in the opposite direction.
The major disadvantage of this technology is linked with the fatigue effect of ferroelectric materials. The residual polarization gradually decreases after a varying number of switching operations. This critical number is typically approximately 10.sup.9 to 10.sup.11 switching cycles. It is consequently not possible to read and write such a memory point more than 10.sup.9 times. It is therefore important to note that such a memory has a longer life on writing than an EEPROM, which can only be read and programmed 10.sup.6 times.
Moreover, these memories are also much faster on writing. Thus, less than 100 nanoseconds are adequate for reversing the polarization direction. However, the life on reading is much shorter than in the case of an EEPROM. To simplify, it can be stated, by comparison with an EEPROM, that a memory produced according to this technology is an essentially programmable or write mostly memory.
To obviate this disadvantage, another variant of cells also using metal-ferroelectric-metal capacitors has been proposed. This is the so-called ferroelectric SRAM memory shown in FIG. 2B and described in the document referred to hereinbefore, namely Review Electronics, as well as in French patent application 4 809 225 filed on Feb. 7, 1987. Such a memory functions like a conventional SRAM with 6 or 4 transistors and as shown in FIG. 1B, without the switching of the ferroelectric capacitors during the read/write cycles. The latter are only subject to action in the case of an interruption to the power supply as a result of an automatic opening of transistors rendered conductive by said interruption. This concept unfortunately suffers from the major disadvantage of the high cost of the memory point, due to the number of transistors and semiconductor surface per memory point.
In addition, the simplest memory structure using a single transistor and a single capacitor per memory point (FRAM cell) requires a quasi-systematic switching. Apart from the life problem, it also suffers from the major disadvantage that it does not tolerate the often significant fluctuations of the charges displaced in the ferroelectric between individual cells or on the same cell during the aging thereof. Thus, taking account of these fluctuations it may become impossible to discriminate between individual polarization states by reading the displaced charge.
It is known from the article by Shu-Yan WU in IEEE Transactions on electron devices, 1974, p. 499 to use a metal-ferroelectric-semiconductor transistor for solving these problems. In this transistor, the ferroelectric replaces the conventional MOS dielectric shown in FIG. 2C, said cell functioning in a similar manner to that of an EEPROM (FIG. 1C).
The ferroelectric is uniformly polarized over its entire surface in a predetermined residual polarization state (state 0). In this state, the transistor, for a chosen reading gate voltage, is in a conductive state. The programming of the complementary state 1 takes place by applying appropriate voltages to the terminals of the ferroelectric by the gate G, the drain D and, if necessary, the substrate, by means of a supplementary substrate, so that at least locally there is a reversal of the residual polarization direction of the ferroelectric. Level with these locations in the semiconductor, as a result of the effect of the induced field, the charges will be repelled and the transistor will be made non-conductive for reading and gate voltage.
The programming voltage on the semiconductor side can either be applied to the transistor drain. There is then a reversal of the polarization solely in the vicinity of the drain, but this is sufficient to block the transistor. This is the simplest version because it is possible to have a point-by-point programming without supplementary contacting. Alternatively it can be applied to the substrate, whilst maintaining the source and drain zones at 0 voltage. There is then a reversal of the ferroelectric on the complete channel zone. However, this requires specific contacting for each transistor, if a point-by-point programming is desired.
The erasing of state 1 takes place by the reverse operation, i.e. by creating an electric field opposite to that created during programming and by reestablishing the initial residual polarization.
Such a memory has a very long life on reading, in the same way as EPROMS and EEPROMS, whilst also having considerably improved speed and life on programming compared with the latter.
However, this structure still suffers from a major shortcoming. The ferroelectric must be in intimate contact with the semiconductor. Thus, the relationship between the permittivity of the ferroelectric and the dielectrics able to form at the ferroelectric/semiconductor interface is such that the complete potential drop takes place in the dielectric, even if the thickness of the latter exceed 1/10 of the total thickness. However, a ferroelectric is not generally chemically stable with standard semiconductors and in particular with silicon. It will therefore react with the latter to form intermediate compounds or certain elements will diffuse on either side of the interface, thus destroying the characteristics of one or other of the materials.
It has also been demonstrated that for a certain number of ferroelectrics there is a charge injection from the semiconductor into the ferroelectric with the trapping of the charges in the latter. The height of the barrier between the semiconductor and the ferroelectric is often inadequate for limiting this injection. The trapped charges often shield the polarization and the field effect induced by the latter. It is therefore necessary to introduce a dielectric material with a very high barrier, but then there is once again the problem of the shielding of the programming field by the latter and the application of excessive programming voltages.
In addition, ferroelectric layers used alone have mediocre breakdown properties. Finally, the ferroelectric has an extremely high apparent dielectric constant, which leads to excessive gate capacitances and to a difficulty of optimizing the transistors.